1. Field of the Invention
The present invention relates to the field of synchronization control in computer systems.
2. Description of Related Art
The closest art known to the Applicant is embodied in the Intel 80386.sup.tm ('386.sup.tm) microprocessor manufactured by Intel Corporation of Santa Clara, Calif.
In general, computer systems utilizing the '386 microprocessor embody a number of components, such as the '386 microprocessor, a math coprocessor (typically either the 80287 or 80387 numeric coprocessor), etc. In computer systems utilizing the '386 processor, the general purpose microprocessor (i.e., the '386) and the math coprocessor are separate, discrete components.
The architecture of the '386, as in many general purpose processors, includes synchronization instructions; such synchronization instruction allow for synchronization of processing between components in a computer system utilizing the '386. Further, synchronization instruction may provide means for initiating error checking.
For example, the WAIT instruction in the '386 instruction set causes the '386 to wait execution until a numeric coprocessor (such as the 80287 or 80387) has finished a task. In general, the numeric coprocessor activates a BUSY pin. When the BUSY pin is active (brought low in the '386), the WAIT instruction suspends execution of '386 instructions until the BUSY pin is inactivated (brought high). In this way, processing on the '386 microprocessor may be suspended to guarantee that a numeric instruction being processed by the numeric coprocessor has completed execution.
It is desired to develop a method for removing (or ignoring during execution) synchronization instructions from an instruction sequence in computer systems.
Specifically, it is desired to develop a system for speeding up the execution of an instruction sequence by removing, under certain conditions, wait states created by synchronization instructions.